The present invention is directed to semiconductor device packaging and, more particularly, to a method of assembling embedded semiconductor die ball grid array packages with a strip or panel form frame.
Fan-out wafer level packages (WLPs) have many advantages, including the provision of a high-number of input/output (I/O) terminals with a smaller package footprint and without wasting valuable silicon real estate on the active die. However, the assembly process is capital intensive and tends to result in packages having a relatively high profile. One of the conventional steps of an assembly process for a fan-out WLP is a spin-on technique for applying a dielectric material. This technique increases the cost because round components are needed for the spin-on processing to effectively embed the die and other components. Spin-on processes are also inefficient with respect to area.
It is therefore desirable to provide a method of assembling low profile semiconductor packages having the advantages of a fan-out WLP.